👋 Hello, I'm Talha Bin Aslam, a PhD Scholar at the VICAS Lab, IIIT-Delhi, working under the supervision of Dr. Anuj Grover. My research is on SRAM memory architectures and modeling for compute-in-memory (CIM), with a focus on accelerating AI and machine learning workloads.
🎓 I earned my M.Tech in Electronics Circuit and System Design from Aligarh Muslim University (CPI 9.08 / 10) in 2021 as a UGC-GATE Scholarship recipient, after completing my B.Tech in Electronics Engineering at the same institution.
🔬 From September 2023 to September 2024, I was a Research Intern at STMicroelectronics, Greater Noida, where I developed behavioral and analytical noise models for SRAM memory subsystems and collaborated with cross-functional silicon and SoC design teams on memory subsystem characterization using Cadence and Synopsys tool flows.
💡 My research interests lie in SRAM bitcell design (6T and custom 10T1C), sense amplifier characterization, peripheral I/O, and Python-based modeling frameworks. I architected AnalogSim, a modeling and verification framework for SRAM-based memory architectures published at IEEE ISCAS 2025.
🏆 I am a recipient of the IEEE SSCS Student Travel Grant ($2,000) to attend ISSCC in San Francisco, and previously the UGC-GATE Scholarship throughout my M.Tech.
The future of computing isn't about moving data faster — it's about not moving data at all. Memory is no longer just storage; it is the engine. Talha Bin Aslam
News and Highlights
| Timeline | News |
|---|---|
| 2026 | Journal paper "An HLS-based Framework for Non-Ideality Aware Modeling of SRAM-based Analog In-Memory Computing Accelerators" accepted at IEEE JETCAS (Journal on Emerging and Selected Topics in Circuits and Systems). |
| 2025 | Awarded the IEEE SSCS Student Travel Grant ($2,000) to attend ISSCC, San Francisco, USA. |
| 2025 | Paper titled "AnalogSim: A Modeling Framework for SRAM-based Analog In-Memory Computing" accepted at IEEE ISCAS 2025, London, UK. |
| 2025 | Paper titled "MeMu-Link: A Simulink Tool for Enhanced Design Exploration of IMC Architectures" accepted at IEEE VDAT. |
| Sep 2024 | Completed one-year Research Internship at STMicroelectronics, Greater Noida (Sep 2023 – Sep 2024). |
| 2024 | Paper titled "Investigating the Impact of Differential Voltage and Sense Amplifier Offset on Power and Delay of SRAM in 65 nm LSTP Technology" accepted at IEEE TENSYMP 2024, New Delhi. |
| Sep 2023 | Joined STMicroelectronics, Greater Noida, as Research Intern for SRAM memory subsystem noise modeling. |
| Jan 2022 | Began PhD in Electronics & Communication Engineering at IIIT-Delhi under Dr. Anuj Grover. |
| 2021 | Published "FPGA Implementation of an Approximate Booth-Wallace Tree Multiplier" at the International Conference on Innovative Computing. |
| 2021 | Completed M.Tech in Electronics Circuit and System Design from Aligarh Muslim University with CPI 9.08 / 10. |
| 2019 | Published first paper "Design and Implementation of Low Cost Digital Timetable for Prayers" at the International Conference on Electrical, Electronics and Computer Engineering. |
| 2019 | Qualified GATE in Electronics & Communication Engineering; awarded the UGC-GATE Scholarship. |
Research Interests
- SRAM-based In-Memory Computing — analog and digital architectures for DNN inference acceleration
- SRAM Bitcell Design — 6T and custom 10T1C cells, stability and yield characterization
- Sense Amplifier Design — offset characterization, differential voltage analysis, low-power optimization
- Memory Subsystem Modeling — behavioral and analytical noise models, Python-based simulation frameworks
- DNN Accelerator Architectures — workload-dependent benchmarking of CIM macros
- Approximate Computing — for machine learning hardware
- Low-Power CMOS Circuit Design — 65 nm LSTP technology, PPA trade-offs
- Custom Memory IP Characterization — DRC/LVS, post-layout extraction, PVT sign-off
Education
- Ph.D. in Electronics & Communication Engineering, IIIT-Delhi · VICAS Lab · Jan 2022 – Present · CPI 8.09 / 10 · Advisor: Dr. Anuj Grover
- M.Tech in Electronics Circuit and System Design, Aligarh Muslim University (AMU), Aligarh · 2019 – 2021 · CPI 9.08 / 10 · UGC-GATE Scholarship
- B.Tech in Electronics Engineering, Aligarh Muslim University (AMU), Aligarh · 2015 – 2019 · CPI 7.16 / 10
Research and Professional Experience
| Timeline | Organisation | Designation | Supervisor | Focus |
|---|---|---|---|---|
| Jan 2022 – Present | IIIT-Delhi (VICAS Lab) | PhD Researcher | Dr. Anuj Grover | SRAM memory architectures and modeling for compute-in-memory; AnalogSim framework; replica I/O peripheral circuits and AOI321 standard cell design in 65 nm LSTP. |
| Sep 2023 – Sep 2024 | STMicroelectronics, Greater Noida | Research Intern | — | Behavioral and analytical noise modeling for SRAM memory subsystems; cross-functional collaboration with silicon and SoC design teams using Cadence and Synopsys tool flows. |
| 2019 – 2021 | Aligarh Muslim University | M.Tech Researcher | — | Electronics Circuit and System Design; UGC-GATE Scholarship recipient. |
Publications
Technical Skills
| Category | Skills |
|---|---|
| Memory Design & Modeling | SRAM bitcell design (6T, custom 10T1C); sense amplifier design and offset characterization; address decoders; write drivers; replica I/O circuits; behavioral and analytical memory modeling; memory subsystem characterization; in-memory computing architectures |
| HDL & Behavioral Modeling | Verilog; SystemVerilog; behavioral model development for memory components; functional verification; modeling at HLS abstraction |
| Programming | Python; C / C++; MATLAB; LaTeX |
| EDA & Simulation Tools | Cadence Virtuoso; Synopsys Design Compiler; ELDO (SPICE); Xilinx Vivado HLS; MATLAB Simulink |
| Verification & Characterization | Functional verification; sign-off simulations; PVT characterization across corners; DRC / LVS; post-layout extraction |
| Low-Power Circuit Design | CMOS low-power techniques; sense amplifier optimization; differential voltage analysis; standard cell layout (AOI321); power / delay trade-off analysis |
| Domain Knowledge | Memory hierarchies; Static Timing Analysis (STA) fundamentals; custom memory IP characterization; accelerator architecture; 65 nm LSTP technology |
Honors and Awards
- IEEE SSCS Student Travel Grant ($2,000), 2025 — Awarded by the IEEE Solid-State Circuits Society to attend the International Solid-State Circuits Conference (ISSCC), San Francisco, USA.
- UGC-GATE Scholarship, 2019 – 2021 — Awarded by the University Grants Commission of India for qualifying GATE; held throughout the M.Tech program at AMU.
- GATE Qualified, 2019 — Qualified the Graduate Aptitude Test in Engineering (GATE) in Electronics & Communication Engineering.